Scroll to Top

# Digital Circuits Questions and Answers – Digital Integrated Circuits – 1

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Digital Integrated Circuits – 1”.

1. Which of the following logic families has the highest maximum clock frequency?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS

Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency of 105 MHz. S-TTL (Schottky High Speed TTL) has 100 MHz. Found nothing as HS-TTL. There are H and S separate TTL. HCMOS has 50 MHz clock frequency.

2. Why is the fan-out of CMOS gates frequency dependent?
a) Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate
b) When the frequency reaches the critical value the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal and this defines the upper operating frequency
c) The higher number of gates attached to the output the more frequently they will have to be serviced thus reducing the frequency at which each will be serviced with an input signal
d) The input gates of the FETs are predominantly capacitive and as the signal frequency increases the capacitive loading also increases thereby limiting the number of loads that may be attached to the output of the driving gate

Explanation: Fan out is the measure of maximum number of inputs that a single logic gate output can drive. Actually power dissipation in CMOS circuits depends on clock frequency. As the frequency increases Pd also increases so fan-out depends on frequency.

3. Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have:
a) A greater current/voltage capability than an ordinary logic circuit
b) Greater input current/voltage capability than an ordinary logic circuit
c) A smaller output current/voltage capability than an ordinary logic
d) Greater the input and output current/voltage capability than an ordinary logic circuit

Explanation: Buffer circuits are usually incorporated to isolate the input from the output. Logic circuits that are designated as buffers, drivers or buffer/drivers are designed to have a greater current/voltage capability than an ordinary logic circuit.

4. Which of the following will not normally be found on a data sheet?
a) Minimum HIGH level output voltage
b) Maximum LOW level output voltage
c) Minimum LOW level output voltage
d) Maximum HIGH level input current

Explanation: Minimum LOW level output voltage will not normally be found on a data sheet.

5. Which of the following logic families has the shortest propagation delay?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS

Explanation: AS-TTL (Advanced Schottky) has a maximum clock frequency that is 105 MHz. So, the propagation delay will be given by 1/105 sec which is the lowest one. It is followed by S-TTL and HCMOS in terms of increasing propagation delay.

6. What is the static charge that can be stored by your body as you walk across a carpet?
a) 300 volts
b) 3000 volts
c) 30000 volts
d) Over 30000 volts

Explanation: When a person walks across a carpeted or tile floor electric charge builds up in the body due to the friction between shoes and floor material. If the friction static is greater the voltage potential develop in the body will be greater. You start act as a capacitor. This is called Electrostatic discharge. The potential static charge that can develop from walking on tile floors is greater than 15000 volts while carpeted floors can generate in excess of 30000 volts.

7. What must be done to interface TTL to CMOS?
a) A dropping resistor must be used on the CMOS of 12 V supply to reduce it to 5 V for the TTL
b) As long as the CMOS supply voltage is 5 V they can be interfaced (however, the fan-out of the TTL is limited to five CMOS gates)
c) A 5 V zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates
d) A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates connected to the node

Explanation: To interface TTL to CMOS a pull-up resistor must be used between the TTL output-CMOS input node and Vcc. A pull-up resistor is used to avoid the floating state on the input node of the CMOS, thus using a small amount of current. The value of RP will depend on the number of CMOS gates connected to the node.

8. What causes low-power Schottky TTL to use less power than the 74XX series TTL?
a) The Schottky-clamped transistor
b) A larger value resistor
c) The Schottky-clamped MOSFET
d) A small value resistor

Explanation: A larger value resistor causes low power low-power Schottky TTL to use less power than the 74XX series TTL.

9. What are the major differences between the 5400 and 7400 series of ICs?
a) The 5400 series are military grade and require tighter supply voltages and temperatures
b) The 5400 series are military grade and allow for a wider range of supply voltages and temperatures
c) The 7400 series are an improvement over the original 5400s
d) The 7400 series was originally developed by Texas Instruments and the 5400 series was brought out by National Semiconductors after TI’s patents expired as a second supply source

Explanation: The 5400 series are military grade and allow for a wider range of supply voltages and temperatures, these are the major differences between the 5400 and 7400 series of ICs. Also, the working temperature range of 5400 series is -50 to 125C while that for 7400 is 0 to 70C.

10. Which of the following statements apply to CMOS devices?
a) The devices should not be inserted into circuits with the power on
b) All tools, test equipment and metal workbenches should be tied to earth ground
c) The devices should be stored and shipped in antistatic tubes or conductive foam
d) All of the Mentioned