Digital Circuits Questions and Answers – MOS Digital Integrated Circuits

Digital Circuits Questions and Answers – MOS Digital Integrated Circuits

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “MOS Digital Integrated Circuits”.

1. The full form of MOS is ___________
a) Metal oxide semiconductor
b) Metal oxygen semiconductor
c) Metallic oxide semiconductor
d) Metallic oxygen semiconductor

Answer: a
Explanation: The full form of MOS is “Metal Oxide Semiconductor”. It is a type of transistor having 3 layers: a metal conductor, an insulating silicon layer and a semiconductor silicon layer.

2. What are the types of MOSFET devices available?
a) P-type enhancement type MOSFET
b) N-type enhancement type MOSFET
c) Depletion type MOSFET
d) All of the mentioned

Answer: d
Explanation: MOSFET are of two types: enhancement and depletion type. Further, these are classified into n-type and p-type device. The depletion type is switched on without the application of gate bias voltage and the enhancement type is switched on with the application of gate voltage.

3. Which insulating layer used in the fabrication of MOSFET?
a) Aluminium oxide
b) Silicon Nitride
c) Silicon dioxide
d) Aluminium Nitrate

Answer: c
Explanation: Silicon dioxide is used as an insulating layer in the fabrication of MOSFET. It gives an extremely high input resistance in the order of 10^10 to 10^15 Ω for MOSFET.

4. Which of the following plays an important role in improving device performance of MOSFET?
a) Dielectric constant
b) Threshold voltage
c) Power supply voltage
d) Gate to drain voltage

Answer: b
Explanation: In MOSFET, the threshold voltage is typically 3 to 6V. This large voltage is not compatible with the supply of 5V which is used in digital ICs. So, for the improvement of the device’s performance the magnitude of threshold voltage should be reduced.

5. A technique used to reduce the magnitude of threshold voltage of MOSFET is the ___________
a) Use of complementary MOSFET
b) Use of Silicon nitride
c) Using thin film technology
d) Increasing potential of the channel

Answer: b
Explanation: Silicon nitride is sandwiched between two SiO2 layer and provide necessary barrier. The dielectric constant of Si3N4 is 7.5, whereas that of SiO2 is 4. This increase in overall dielectric constant reduces threshold voltage.

6. What is used to higher the speed of operation in MOSFET fabrication?
a) Ceramic gate
b) Silicon dioxide
c) Silicon nitride
d) Poly silicon gate

Answer: d
Explanation: In conventional metal gate small overlap capacitance is present, which lowers the speed of operation. With the presence of self aligning property of the poly silicon gate it eliminates this capacitance. Using a process called ion-implantation, polysilicon, the drain and the source get doped. However, the thin oxide under silicon gate acting as a mask for the process and thus develops the gate aligning property.

7. Find the sequence of steps involved in fabrication of poly silicon gate MOSFET?
Step 1: Entire wafer surface of a Si3N4 is coated and is etched away with the help of mask to include source, gate and drain.
Step 2: The contact areas are defined using photolithographic process.
Step 3: Selective etching of Si3N4 and growth of thin oxide.
Step 4: The deposition of poly silicon gate.
Step 5: The growth of thick oxide is called field oxide and P implantation.
Step 6: The metallization and interconnection between substrate and source.
a) 1->5->3->4->2->6
b) 1->3->4->2->5->6
c) 1->5->4->3->2->6
d) 1->4->2->5->3->6

Answer: a
Explanation: These steps are the sequence of steps involved in fabrication of poly silicon gate MOSFET. With the help of poly silicon gate doping, it highers the speed of operation of the MOSFET.

8. Why MOSFET is preferred over BJT in IC components?
a) MOSFET has low packing density
b) MOSFET has medium packing density
c) MOSFET has high packing density
d) MOSFET has no packing density

Answer: a
Explanation: MOSFET is preferred over BJT because of its low packaging density. Thus, more number of MOSFET memory cells can be accommodated in a particular area as compared to BJT.

9. Critical defects per unit chip area is ________ for a MOS transistor.
a) High
b) Low
c) Neutral
d) Very High

Answer: b
Explanation: Critical defects per unit chip area is low for a MOS transistor because it involves fewer steps in the fabrication of a MOS transistor. Also, MOSFET has low packaing density.

10. MOS is being used in ___________
a) LSI
b) VLSI
c) MSI
d) Both LSI and VLSI

Answer: d
Explanation: Since more transistor and circuitry functions can be achieved on a single chip with MOS technology that is why MOS is being used in LSI and VLSI. LSI stands for Large Scale Integration and VLSI stands for Very Large Scale Integration.

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