Digital Circuits Questions and Answers – Emitter-Coupled Logic(ECL)

Digital Circuits Questions and Answers – Emitter-Coupled Logic(ECL)

 

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Emitter-Coupled Logic(ECL)”.

1. The full form of ECL is __________
a) Emitter-collector logic
b) Emitter-complementary logic
c) Emitter-coupled logic
d) Emitter-cored logic

Answer: c
Explanation: The full form of ECL is emitter-coupled logic.

2. Which logic is the fastest of all the logic families?
a) TTL
b) ECL
c) HTL
d) DTL

Answer: b
Explanation: ECL is the fastest of all the logic families because of the emitters of many transistors are coupled together which results in the highest transmission rate.

3. The full form of CML is __________
a) Complementary mode logic
b) Current mode logic
c) Collector mode logic
d) Collector Mixed Logic

Answer: c
Explanation: The full form of CML is Collector Mode Logic.

4. Sometimes ECL can also be named as __________
a) EEL
b) CEL
c) CML
d) CCL

Answer: c
Explanation: ECL (Emitter Coupled Logic) can also be named as CML(Collector Mode Logic).

5. In an ECL the output is taken from __________
a) Emitter
b) Base
c) Collector
d) Junction of emitter and base

Answer: c
Explanation: Though, the emitter and collector of the ECL are coupled together. So, the output will be taken from a collector.

6. The ECL behaves as __________
a) NOT gate
b) NOR gate
c) NAND gate
d) AND gate

Answer: b
Explanation: The ECL behaves as NOR gate because if any of the input voltages go high as compared to the reference voltage, the output is low and the output is high only when all the input voltages are low.

7. In ECL the fanout capability is __________
a) High
b) Low
c) Zero
d) Sometimes high and sometimes low

Answer: a
Explanation: If the input impedance is high and the output resistance is low; as a result, the transistors change states quickly, gate delays are low, and the fanout capability is high. Fan-out is the measure of the maximum number of inputs that a single gate output can accept.

8. ECL’s major disadvantage is that __________
a) It requires more power
b) It’s fanout capability is high
c) It creates more noise
d) It is slow

Answer: a
Explanation: ECL’s major disadvantage is that each gate continuously draws current, which means it requires (and dissipates) significantly more power than those of other logic families. But ECL logic gates have clock frequency. Thus, they have a fast operation.

9. The full form of SCFL is __________
a) Source-collector logic
b) Source-coupled logic
c) Source-complementary logic
d) Source Cored Logic

Answer: b
Explanation: The full form of SCFL is source-coupled logic.

10. The equivalent of emitter-coupled logic made out of FETs is called __________
a) CML
b) SCFL
c) FECL
d) EFCL

Answer: b
Explanation: The equivalent of emitter-coupled logic made out of FETs is called Source-coupled logic(SCFL). Like ECL, SCL is also the fastest among the logic families.

11. ECL was invented in _______ by __________
a) 1956, Baker clamp
b) 1976, James R. Biard
c) 1956, Hannon S. Yourke
d) 1976, Yourke

Answer: c
Explanation: ECL was invented in August 1956 at IBM by Hannon S Yourke.

12. At the time of invention, an ECL was called as __________
a) Source-coupled logic
b) Current Mode Logic
c) Current-steering logic
d) Emitter-coupled logic

Answer: c
Explanation: At the time of invention, an ECL was called as current-steering logic because it involved current switching.

13. The ECL circuits usually operates with __________
a) Negative voltage
b) Positive voltage
c) Grounded voltage
d) High Voltage

Answer: a
Explanation: The ECL circuits usually operate with negative power supplies (positive end of the supply is connected to ground), in comparison to other logic families in which negative end of the supply is grounded. It is done mainly to minimize the influence of the power supply variations on the logic levels as ECL is more sensitive to noise on the VCC and relatively immune to noise on VEE.

14. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of __________
a) ECL
b) VECL
c) PECL
d) LECL

Answer: c
Explanation: Low voltage positive emitter coupled logic (LVPECL) is a power optimized version of PECL using a +3.3 V instead of 5 V supply.

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